High quality audio power amplifiers are traditionally large, heavy, and inefficient. Typically these equipments are capable of high power audio output with very low total harmonic distortion (THD). However, these equipments achieve only approximately 25% efficiency under normal audio operating conditions because they typically use inefficient linear or quasi-linear amplifiers (e.g. Class A, B, G, and H).
In recent years, the demand for more efficient audio power amplifiers has increased. Thus the shift from Class B to Class D amplifiers for sound reproduction.
Class D amplifiers provide high efficiency, but typically have limited bandwidths, resulting in high THD at high audio frequencies.
A Class D amplifier is basically a switch-mode power supply modified to operate in four quadrants at high frequencies (e.g. audio frequencies). A switch-mode power supply uses pulse-width modulation (PWM) to control the ON/OFF duty cycle of power switching transistor(s) that provide power to a load. The efficiency is high because the switches are not operated in their linear region.
FIG. 1 is an illustration of a simplified Class D topology. As illustrated, a comparator circuit (not shown) inside the Pulse-Width Modulator 110 compares the amplitude of incoming analog audio signal 101 to the amplitude of a reference triangular waveform operating at an intended switching frequency. The comparator circuit switches its output high or low by comparing the incoming audio's amplitude against the amplitude of the triangular waveform. When audio signal 101 is above the amplitude of the triangular waveform, the comparator switches output D+ of the PWM 110 to the ON state. Output D+ remains ON for the duration of time while the input audio signal exceeds the amplitude of the triangular waveform. Conversely, while the input audio signal is below the amplitude of the triangular waveform, the output D+ of the PWM is at the OFF state. Output D− is the inverse, i.e., complementary of output D+.
The relationship between the input audio amplitude and the pulse-width modulator outputs D+, and D− is linear to a first order. The outputs D+ and D− of the comparator drive “totem-poled” transistor switches Q1 and Q2. Each transistor switch is a MOSFET device, with a diode device 131 coupled across its terminals to enable four quadrant switching. The topology shown in FIG. 1 is an example embodiment of a class D amplifier where the same type MOSFETs is used for both switches. Alternate embodiments include using complementary transistors, e.g. one p-type and one n-type MOSFET. For this reason the MOSFET symbol used shows no polarity.
Output filter 140 is typically a second order low-pass, e.g., LC configuration filter. The output filter 140 is essential for low pass filtering, or integrating, the carrier's varying pulse width duty cycle for reproduction of the original audio content while attenuating the switching carrier frequency.
For high fidelity audio reproduction, the operating (i.e. switching) frequency of the Class D power amplifier must be significantly higher than the bandwidth of the audio being reproduced. Thus, to reproduce higher bandwidth audio with higher fidelity requires relatively high switching frequency. However, the higher the switching frequency, the more the switching losses (i.e. reduced efficiency). Some causes of switching losses are discussed using the illustration in FIG. 2.
FIG. 2 is an illustration of a conventional Half Bridge Class D Amplifier with salient parasitic elements. As illustrated, voltage source VgsQ1 drives the gate of transistor Q1 and voltage source VgsQ2 drives the gate of transistor Q2. The illustration is a standard half-bridge showing parasitic elements CQ1, which is the intrinsic capacitance of transistor Q1; and CQ2, which is the intrinsic capacitance of transistor Q2. Element D1 is either Q1's intrinsic diode or an external diode with lower drop; and element D2 is either Q2's intrinsic diode or an external diode with lower drop. The currents and direction of flow (i.e. drain to source) are shown with the double arrows.
In this illustration, transistors Q1 and Q2 supply a quasi-square wave to the filter formed by output inductor L1 and output capacitor C1. Node 201, shared commonly by transistors Q1, Q2, and inductor L1 is referred herein as the switching node. During operation, the voltage at switching node 201 is a square wave represented by waveform 310, as shown in FIG. 3. This voltage is low-pass filtered by the output LC filter comprised of inductor L1 and capacitor C1 to produce a relatively low frequency output voltage across capacitor C1.
The inductor current (IL1) at idle, that is, at zero output voltage, is represented by the triangular waveform 320 of FIG. 3. Triangular waveform 320 is a ripple current which produces a quasi-sinusoidal ripple voltage, i.e. waveform 330 of FIG. 3, on output capacitor C1. This output ripple voltage, i.e. 330, must be limited in magnitude or there can be problems with radiated emissions. For this reason the value of the output inductor L1 is kept high enough to limit the ripple current to some small fraction of the full power output current, typically 20% as a rule of thumb. FIG. 4 is an illustration of the relationship between ripple current and load current.
As illustrated in FIG. 4, the current at idle is shown by waveform 410 while the current at ⅛ power is shown by waveform 420. As shown in both waveforms 410 and 420, the ripple characteristic causes a non-steady disturbance in the output current about the steady state value. At idle, the average current is zero and the ripple characteristic of the Class D results in the non-steady negative and positive current oscillations. Since the amplitude of the oscillation (i.e. ripple) is controlled by the size of inductor L1, similar ripple amplitude exists at other load values. For instance, as illustrated in waveform 420, the steady state current at ⅛ power is represented by the current value IL1DC and the ripple current superimposes thereon with ripple amplitude of approximately 20% peak to peak around the ⅛ power load current value IL1DC.
Thus, although there are no intentionally dissipative elements in the circuit shown in FIG. 2, the practical circuit will not be 100% efficient because of a variety of finite loss mechanisms therein. For instance, there are inherent losses in the output LC filter and in the switching transistors. Losses in the filter section are well understood and chosen as a cost tradeoff, but losses in the transistors (FETs) have more constraints. Firstly, FETs Q1 and Q2 will have a finite ON resistance, leading to conduction loss. Secondly, Q1 and Q2 will experience some loss at switching transitions, leading to switching losses. It is these switching losses that primarily limit the switching frequency. Thus, even though a higher switching frequency (audio bandwidth) would be generally beneficial to audio performance, it also results in lower efficiency; therefore, prior art systems tradeoff bandwidth for efficiency.
With the approximately 20% current ripple of the prior art conventional Class D amplifier, a lossy (or hard) switching transition exists when output current is high. This lossy switching transition of the conventional Class D amplifier is illustrated using the waveforms of FIG. 14.
As illustrated, starting with Q2 in the ON state (i.e. the gate supply voltage VgsQ2 1402 is greater than the threshold value) and a large positive current, IL1 1403, flowing through inductor L1. The inductor current IL1 1403 flows through Q2's ON resistance from source to drain, which is a negative value represented by IdsQ2 1404.
At time t1, Q2 is turned OFF and the inductor current IL1 moves from Q2's ON resistance to D2, which is either Q2's intrinsic diode or an external diode with lower drop. The voltage across Q2, i.e. VdsQ2 1406, cannot rise until time t2, when Q1 turns ON, but this will cause a large reverse recovery current (ID2 1405) to flow through D2 and Q1, since D2 has a finite turn off time represented by the period between t2 and t3. Thus, the reverse recovery period lasts until time t3. Therefore, from t2 to t3, transistor Q1 sees high current (ID2 1405) and high voltage (VdsQ2 1406) simultaneously, the product of which will be high switching loss (i.e. dissipated power).
Thus, improvement in efficiency can be realized with reduction in switching losses. Alternately, the switching frequency could be raised to realize improved performance without reducing efficiency. But this could not be done in conventional Class D amplifiers without increasing high frequency ripple.
Although the high frequency ripple is generally inaudible to the human ear, its presence is still undesirable for several reasons: (1) it is an emissions problem, for instance, it appears as artifacts in the AM radio band and other places; (2) it influences audio measurements; (3) provides a limitation on how clean the output signal looks to the end user; and (4) puts unwanted artifacts on a feedback signal fed to the control circuit, limiting the performance. Thus, any solution to reduce switching losses must also address high frequency ripple.
As discussed above, waveform 330 clearly shows the ripple phenomenon. In practice the voltage ripple on a full bandwidth class D amplifier can be on the order of one volt peak-to-peak with a fundamental of several hundred kHz, making it extremely prone to interfering with other electronic equipment, especially AM radio receivers. Modulation schemes in which the switching frequency is variable are particularly troublesome.
Prior art methods to reduce ripple includes using an LC series trap circuit across the output capacitor C1. This approach has several disadvantages. First, the Q (quality factor) of the LC trap must be extremely high in order to effectively shunt current away from C1, whose impedance at the switching frequency is already well below an Ohm. Second, the trap is only effective at a single frequency. The higher the Q, the less effective the trap will be if the switching frequency is variable. The trap is also not very effective at attenuating harmonics of the switching frequency; although these are usually 20 dB down from the fundamental in relative terms, they can still present problems if their magnitude is too large in absolute terms.
Another prior art method of reducing ripple would be to add another second order filter to the output, creating a fourth order filter. Some of the disadvantages of this method include that the inductor must be sized to handle the full output current, and the filter may add distortion due to nonlinearity in the devices used, and the filtered output is outside of the control of any feedback loop.
Another prior art method to handling the ripple problem is to add a second LC low-pass filter in the output thus effectively increasing the order of the output filter from two to four. However, fourth order filters pose controllability and linearity problems. In addition, the higher order filter increases the total harmonic distortion (THD).
The present invention teaches reduction of switching losses while reducing the effect of ripple to acceptable levels.